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C/C++ Source or Header  |  1999-09-17  |  4KB  |  95 lines
  1. /*
  2.  * include/asm-arm/dec21285.h
  3.  *
  4.  * Copyright (C) 1998 Russell King
  5.  *
  6.  * DC21285 registers
  7.  */
  8. #define DC21285_PCI_IACK        0x79000000
  9. #define DC21285_ARMCSR_BASE        0x42000000
  10. #define DC21285_PCI_TYPE_0_CONFIG    0x7b000000
  11. #define DC21285_PCI_TYPE_1_CONFIG    0x7a000000
  12. #define DC21285_OUTBOUND_WRITE_FLUSH    0x78000000
  13. #define DC21285_FLASH            0x41000000
  14. #define DC21285_PCI_IO            0x7c000000
  15. #define DC21285_PCI_MEM            0x80000000
  16.  
  17. #ifndef __ASSEMBLY__
  18. #define DC21285_IO(x)        ((volatile unsigned long *)(0xfe000000+(x)))
  19. #else
  20. #define DC21285_IO(x)        (x)
  21. #endif
  22.  
  23. #define CSR_PCICMD        DC21285_IO(0x0004)
  24. #define CSR_PCICACHELINESIZE    DC21285_IO(0x000c)
  25. #define CSR_PCICSRBASE        DC21285_IO(0x0010)
  26. #define CSR_PCICSRIOBASE    DC21285_IO(0x0014)
  27. #define CSR_PCISDRAMBASE    DC21285_IO(0x0018)
  28. #define CSR_PCIROMBASE        DC21285_IO(0x0030)
  29. #define CSR_CSRBASEMASK        DC21285_IO(0x00f8)
  30. #define CSR_CSRBASEOFFSET    DC21285_IO(0x00fc)
  31. #define CSR_SDRAMBASEMASK    DC21285_IO(0x0100)
  32. #define CSR_SDRAMBASEOFFSET    DC21285_IO(0x0104)
  33. #define CSR_ROMBASEMASK        DC21285_IO(0x0108)
  34. #define CSR_SDRAMTIMING        DC21285_IO(0x010c)
  35. #define CSR_SDRAMADDRSIZE0    DC21285_IO(0x0110)
  36. #define CSR_SDRAMADDRSIZE1    DC21285_IO(0x0114)
  37. #define CSR_SDRAMADDRSIZE2    DC21285_IO(0x0118)
  38. #define CSR_SDRAMADDRSIZE3    DC21285_IO(0x011c)
  39. #define CSR_I2O_INFREEHEAD    DC21285_IO(0x0120)
  40. #define CSR_I2O_INPOSTTAIL    DC21285_IO(0x0124)
  41. #define CSR_I2O_OUTPOSTHEAD    DC21285_IO(0x0128)
  42. #define CSR_I2O_OUTFREETAIL    DC21285_IO(0x012c)
  43. #define CSR_I2O_INFREECOUNT    DC21285_IO(0x0130)
  44. #define CSR_I2O_OUTPOSTCOUNT    DC21285_IO(0x0134)
  45. #define CSR_I2O_INPOSTCOUNT    DC21285_IO(0x0138)
  46. #define CSR_SA110_CNTL        DC21285_IO(0x013c)
  47. #define CSR_PCIADDR_EXTN    DC21285_IO(0x0140)
  48. #define CSR_PREFETCHMEMRANGE    DC21285_IO(0x0144)
  49. #define CSR_XBUS_CYCLE        DC21285_IO(0x0148)
  50. #define CSR_XBUS_IOSTROBE    DC21285_IO(0x014c)
  51. #define CSR_DOORBELL_PCI    DC21285_IO(0x0150)
  52. #define CSR_DOORBELL_SA110    DC21285_IO(0x0154)
  53. #define CSR_UARTDR        DC21285_IO(0x0160)
  54. #define CSR_RXSTAT        DC21285_IO(0x0164)
  55. #define CSR_H_UBRLCR        DC21285_IO(0x0168)
  56. #define CSR_M_UBRLCR        DC21285_IO(0x016c)
  57. #define CSR_L_UBRLCR        DC21285_IO(0x0170)
  58. #define CSR_UARTCON        DC21285_IO(0x0174)
  59. #define CSR_UARTFLG        DC21285_IO(0x0178)
  60. #define CSR_IRQ_STATUS        DC21285_IO(0x0180)
  61. #define CSR_IRQ_RAWSTATUS    DC21285_IO(0x0184)
  62. #define CSR_IRQ_ENABLE        DC21285_IO(0x0188)
  63. #define CSR_IRQ_DISABLE        DC21285_IO(0x018c)
  64. #define CSR_IRQ_SOFT        DC21285_IO(0x0190)
  65. #define CSR_FIQ_STATUS        DC21285_IO(0x0280)
  66. #define CSR_FIQ_RAWSTATUS    DC21285_IO(0x0284)
  67. #define CSR_FIQ_ENABLE        DC21285_IO(0x0288)
  68. #define CSR_FIQ_DISABLE        DC21285_IO(0x028c)
  69. #define CSR_FIQ_SOFT        DC21285_IO(0x0290)
  70. #define CSR_TIMER1_LOAD        DC21285_IO(0x0300)
  71. #define CSR_TIMER1_VALUE    DC21285_IO(0x0304)
  72. #define CSR_TIMER1_CNTL        DC21285_IO(0x0308)
  73. #define CSR_TIMER1_CLR        DC21285_IO(0x030c)
  74. #define CSR_TIMER2_LOAD        DC21285_IO(0x0320)
  75. #define CSR_TIMER2_VALUE    DC21285_IO(0x0324)
  76. #define CSR_TIMER2_CNTL        DC21285_IO(0x0328)
  77. #define CSR_TIMER2_CLR        DC21285_IO(0x032c)
  78. #define CSR_TIMER3_LOAD        DC21285_IO(0x0340)
  79. #define CSR_TIMER3_VALUE    DC21285_IO(0x0344)
  80. #define CSR_TIMER3_CNTL        DC21285_IO(0x0348)
  81. #define CSR_TIMER3_CLR        DC21285_IO(0x034c)
  82. #define CSR_TIMER4_LOAD        DC21285_IO(0x0360)
  83. #define CSR_TIMER4_VALUE    DC21285_IO(0x0364)
  84. #define CSR_TIMER4_CNTL        DC21285_IO(0x0368)
  85. #define CSR_TIMER4_CLR        DC21285_IO(0x036c)
  86.  
  87. #define TIMER_CNTL_ENABLE    (1 << 7)
  88. #define TIMER_CNTL_AUTORELOAD    (1 << 6)
  89. #define TIMER_CNTL_DIV1        (0)
  90. #define TIMER_CNTL_DIV16    (1 << 2)
  91. #define TIMER_CNTL_DIV256    (2 << 2)
  92. #define TIMER_CNTL_CNTEXT    (3 << 2)
  93.  
  94.  
  95.